Software-based register file vulnerability reduction for embedded processors
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
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This paper presents a soft error-tolerant architecture to protect embedded processors register files. The proposed architecture is based on selectively duplication of the most vulnerable registers values in a cache memory embedded beside the processor register file so called register cache. To do this, two parity bits are added to each register of the processor to detect up to three contiguous errors. To recover the erroneous register value, two distinct cache memories are utilized for storing the redundant copy of the vulnerable registers, one for short lived registers and the other one for long lived registers. The proposed method has two key advantageous as compared to fully ECC protected register file:1) the proposed architecture corrects up to three contiguous errors while the ECC protected register file just corrects one bit error, and 2) the proposed architecture consumes about 25% less power than the fully ECC protected register file. The experimental results show that the AVF of the unprotected register file is improved about 90% by the proposed architecture while having a little area overhead.