QPACE: Quantum Chromodynamics Parallel Computing on the Cell Broadband Engine

  • Authors:

  • Gottfried Goldrian;Thomas Huth;Benjamin Krill;Jack Lauritsen;Heiko Schick;Ibrahim Ouda;Simon Heybrock;Dieter Hierl;Thilo Maurer;Nils Meyer;Andreas Schäfer;Stefan Solbrig;Thomas Streuer;Tilo Wettig;Dirk Pleiter;Karl-Heinz Sulanke;Frank Winter;Hubert Simma;Sebastiano Fabio Schifano;Raffaele Tripiccione;Andrea Nobile;Matthias Drochner;Thomas Lippert;Zoltan Fodor

  • Affiliations:

  • IBM Research and Development Lab, Böblingen, Germany;IBM Research and Development Lab, Böblingen, Germany;IBM Research and Development Lab, Böblingen, Germany;IBM Research and Development Lab, Böblingen, Germany;IBM Research and Development Lab, Böblingen, Germany;IBM Systems and Technology Group;University of Regensburg, Germany;University of Regensburg, Germany;University of Regensburg, Germany;University of Regensburg, Germany;University of Regensburg, Germany;University of Regensburg, Germany;University of Regensburg, Germany;University of Regensburg, Germany;Deutsches Elektronen Synchrotron;Deutsches Elektronen Synchrotron;Deutsches Elektronen Synchrotron;University of Milano-Bicocca, Italy;University of Ferrara, Italy;University of Ferrara, Italy;European Center for Theoretical Studies, Trento, Italy;Research Center Julich, Gernany;Research Center Julich, Gernany;University of Wuppertal, Germany

  • Venue:
  • Computing in Science and Engineering
  • Year:
  • 2008

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Abstract

The Quantum Chromodynamics Parallel Computing on the Cell Broadband Engine (QPACE) project is developing a massively parallel, scalable supercomputer for applications in lattice quantum chromodynamics (QCD). Specifically, the architecture is a 3D torus of identical processing nodes, based on the PowerXCell 8i processor. These nodes are tightly coupled by an application-optimized network processor that is based on a field-programmable gate array attached to the PowerXCell 8i. The authors have analyzed lattice QCD code performance on QPACE, carried out corresponding hardware benchmarks, and found that it offers suitable performance. They describe the QPACE architecture in detail, focusing on the challenges arising from the PowerXCell 8i's multicore nature and the use of an FPGA for the network processor.