SCI: Scalable Coherent Interface, Architecture and Software for High-Performance Compute Clusters
SCI: Scalable Coherent Interface, Architecture and Software for High-Performance Compute Clusters
Performance Comparison of MPI Implementations over InfiniBand, Myrinet and Quadrics
Proceedings of the 2003 ACM/IEEE conference on Supercomputing
Can Memory-Less Network Adapters Benefit Next-Generation InfiniBand Systems?
HOTI '05 Proceedings of the 13th Symposium on High Performance Interconnects
POWER5 System microarchitecture
IBM Journal of Research and Development - POWER5 and packaging
HOTI '07 Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects
Architectural support for user-level network interfaces in heavily virtualized systems
WIOV'10 Proceedings of the 2nd conference on I/O virtualization
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Network processors use highly parallel architectures to improve performance and reach multi-gigabit line-speeds. In this paper, we emulate a pipeline in a highly parallel non-programmable industrial InfiniBand Host Channel Adapter to make a performance and bottleneck analysis and, at the same time, explore the potential of a pipelined architecture. Therefore, starting from the original Host Channel Adapter model with multiple send- and receive-side packet-processing units, we compare its performance capabilities with that of a pipelined design by introducing a central arbiter synchronizing the state machines of the different packet-processing instances to achieve a pipelined behavior. We show that the pipelined model achieves a performance comparable to that of the parallel design in most of our micro-benchmarks, making it a valid option for next-generation high-speed adapters. At the same time, our approach enables a deeper analysis of the original architecture and a better understanding of the actual processing requirements, and therefore offers valuable insights for future designs.