Reconfigurable mesh algorithms for the Hough transform
Journal of Parallel and Distributed Computing
Distributed computation with communication delays: asymptotic performance analysis
Journal of Parallel and Distributed Computing
Using MPI: portable parallel programming with the message-passing interface
Using MPI: portable parallel programming with the message-passing interface
Scheduling divisible jobs on hypercubes
Parallel Computing
Scheduling divisible loads in a three-dimensional mesh of processors
Parallel Computing
Scheduling a divisible task in a two-dimensional toroidal mesh
Proceedings of the third international conference on Graphs and optimization
Scheduling Divisible Loads in Parallel and Distributed Systems
Scheduling Divisible Loads in Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
Static Global Scheduling for Optimal Computer Vision and Image Processing Operations on Distributed-Memory Multiprocessor
Scheduling Strategies for Master-Slave Tasking on Heterogeneous Processor Platforms
IEEE Transactions on Parallel and Distributed Systems
A Multistage Load Distribution Strategy for Three-Dimensional Meshes
Cluster Computing
Parallel Implementation of Back-Propagation Algorithm in Networks of Workstations
IEEE Transactions on Parallel and Distributed Systems
Security evaluation of generalized patchwork algorithm from cryptanalytic viewpoint
KES'05 Proceedings of the 9th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part I
The master-slave paradigm with heterogeneous processors
IEEE Transactions on Parallel and Distributed Systems
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In this paper, we propose a new load distribution strategy called 'send-and-receive' for scheduling divisible loads, in a linear network of processors with communication delay. This strategy is designed to optimally utilize the network resources and thereby minimizes the processing time of entire processing load. A closed-form expression for optimal size of load fractions and processing time are derived when the processing load originates at processor located in boundary and interior of the network. A condition on processor and link speed is also derived to ensure that the processors are continuously engaged in load distributions. This paper also presents a parallel implementation of 'digital watermarking problem' on a personal computer-based Pentium Linear Network (PLN) topology. Experiments are carried out to study the performance of the proposed strategy and results are compared with other strategies found in literature.