Identity-based cryptosystems and signature schemes
Proceedings of CRYPTO 84 on Advances in cryptology
Resistance against Differential Power Analysis for Elliptic Curve Cryptosystems
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
A Scalable Architecture for Montgomery Multiplication
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Hardware Implementation of Finite Fields of Characteristic Three
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Dual-Field Arithmetic Unit for GF(p) and GF(2m)
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A Scalable Dual-Field Elliptic Curve Cryptographic Processor
IEEE Transactions on Computers
Efficient Multiplication in GF(pk) for Elliptic Curve Cryptography
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
Data Dependent Power Use in Multipliers
ARITH '05 Proceedings of the 17th IEEE Symposium on Computer Arithmetic
Efficient GF(pm) arithmetic architectures for cryptographic applications
CT-RSA'03 Proceedings of the 2003 RSA conference on The cryptographers' track
Efficient hardware for the tate pairing calculation in characteristic three
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Finite field arithmetic for cryptography
IEEE Circuits and Systems Magazine
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We present a novel unified core design which is extended to realize Montgomery multiplication in the fields GF(2^n), GF(3^m), and GF(p). Our unified design supports RSA and elliptic curve schemes, as well as the identity-based encryption which requires a pairing computation on an elliptic curve. The architecture is pipelined and is highly scalable. The unified core utilizes the redundant signed digit representation to reduce the critical path delay. While the carry-save representation used in classical unified architectures is only good for addition and multiplication operations, the redundant signed digit representation also facilitates efficient computation of comparison and subtraction operations besides addition and multiplication. Thus, there is no need for a transformation between the redundant and the non-redundant representations of field elements, which would be required in the classical unified architectures to realize the subtraction and comparison operations. We also quantify the benefits of the unified architectures in terms of area and critical path delay. We provide detailed implementation results. The metric shows that the new unified architecture provides an improvement over a hypothetical non-unified architecture of at least 24.88%, while the improvement over a classical unified architecture is at least 32.07%.