A mechanically verified language implementation
Journal of Automated Reasoning
VLISP: a verified implementation of Scheme
Lisp and Symbolic Computation
The design and implementation of a certifying compiler
PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
A certifying compiler for Java
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Simple on-the-fly automatic verification of linear temporal logic
Proceedings of the Fifteenth IFIP WG6.1 International Symposium on Protocol Specification, Testing and Verification XV
From States to Transitions: Improving Translation of LTL Formulae to Büchi Automata
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Automata-Based Verification of Temporal Properties on Running Programs
Proceedings of the 16th IEEE international conference on Automated software engineering
SPOT: An Extensible Model Checking Library Using Transition-Based Generalized Büchi Automata
MASCOTS '04 Proceedings of the The IEEE Computer Society's 12th Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
Annotation Inference for Safety Certification of Automatically Generated Code (Extended Abstract)
ASE '06 Proceedings of the 21st IEEE/ACM International Conference on Automated Software Engineering
Proving the shalls: Early validation of requirements through formal methods
International Journal on Software Tools for Technology Transfer (STTT) - A View from Formal Methods 2003 (pp 301-354); Special Section on Recent Advances in Hardware Verification (pp 355-447)
The verifying compiler: a grand challenge for computing research
CC'03 Proceedings of the 12th international conference on Compiler construction
Model-based safety analysis of simulink models using SCADE design verifier
SAFECOMP'05 Proceedings of the 24th international conference on Computer Safety, Reliability, and Security
Verifying semantic conformance of state machine-to-java code generators
MODELS'10 Proceedings of the 13th international conference on Model driven engineering languages and systems: Part I
Verification tool of software requirement for network software
ICICA'11 Proceedings of the Second international conference on Information Computing and Applications
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Within the context of model-based development, the correctness of code generators for modeling notations such as Simulink and Stateflow is of obvious importance. If correctness of code generation can be shown, the extensive and often costly verification and validation activities conducted in the modeling domain could be effectively leveraged in the code domain. Unfortunately, most code generators in use today give no guarantees of correctness.In this paper, we investigate a method of leveraging existing model checking tools to verify the partial correctness of code generated by code generators that offer no guarantees of correctness. We explore the feasibility of this approach through a prototype tool that allows us to verify that Linear Temporal Logic (LTL) safety properties are preserved by C code generators for Simulink models. We find that the approach scales well, allowing us to verify that 55 LTL properties are maintained when generating 12,000+ lines of C code from a large Simulink model.