Run-Time Parallelization and Scheduling of Loops
IEEE Transactions on Computers
The Omega test: a fast and practical integer programming algorithm for dependence analysis
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Improving the performance of runtime parallelization
PPOPP '93 Proceedings of the fourth ACM SIGPLAN symposium on Principles and practice of parallel programming
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
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PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
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Proceedings of the seventh ACM SIGPLAN symposium on Principles and practice of parallel programming
High Performance Compilers for Parallel Computing
High Performance Compilers for Parallel Computing
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Proceedings of the 1994 ACM/IEEE conference on Supercomputing
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Interprocedural parallelization using memory classification analysis
Interprocedural parallelization using memory classification analysis
Hybrid analysis: static & dynamic memory reference analysis
International Journal of Parallel Programming
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Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques
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Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
Sensitivity analysis for automatic parallelization on multi-cores
Proceedings of the 21st annual international conference on Supercomputing
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Sensitivity Analysis (SA) is a novel compiler technique that complements, and integrates with, static automatic parallelization analysis for the cases when program behavior is input sensitive. SA can extract all the input dependent, statically unavailable, conditions for which loops can be dynamically parallelized. SA generates a sequence of sufficient conditions which, when evaluated dynamically in order of their complexity, can each validate the dynamic parallel execution of the corresponding loop. While SA's principles are fairly simple, implementing it in a real compiler and obtaining good experimental results on benchmark codes is a difficult task. In this paper we present some of the most important implementation issues that we had to overcome in order to achieve a fairly successful automatic parallelizer. We present techniques related to validating dependence removing transformations, e.g., privatization or pushback parallelization, and static and dynamic evaluation of complex conditions for loop parallelization. We concern ourselves with multi-version and parallel code generation as well as the use of speculative parallelization when other, less costly options fail. We present a summary table of the contributions of our techniques to the successful parallelization of 22 industry benchmark codes. We also report speedups and parallel coverage of these codes on two multicore based systems and compare them to results obtained by the Ifort compiler.