GP-based design and optimization of a floating voltage source for low-power and highly tunable OTA applications

Authors:
Maryam Shojaei Baghini;Rajendra Kanphade;D. G. Wakade;Priti Gawande;Manisha Chhangani;Manish Patil
Affiliations:
EE Department of IIT Bombay, India;VLSI & Embedded System Design Center, SSGMCE, Shegaon, India;VLSI & Embedded System Design Center, SSGMCE, Shegaon, India;VLSI & Embedded System Design Center, SSGMCE, Shegaon, India;VLSI & Embedded System Design Center, SSGMCE, Shegaon, India;VLSI & Embedded System Design Center, SSGMCE, Shegaon, India
Venue:
WSEAS Transactions on Circuits and Systems
Year:
2008

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Abstract

Reuse of analog building blocks is a time consuming process as CMOS technology scales down. Therefore automatic sizing while taking care of second order effects is of great importance. In this paper a method for automatic sizing and optimization of a floating voltage source (FVS) used in a CMOS Operational Transconductance Amplifier (OTA) is presented. The optimization determines the optimal component values and transistor dimensions for FVS in order to minimize the dissipated power and output impedance. The presented methodology uses geometric programming (GP) and simulation-based optimization in a time-efficient manner. The CMOS FVS is sized initially using convex optimization. Then the design is further optimized by a simulation-based circuit optimizer to include second order effects. Since the initial design uses GP method a globally optimum solution is obtained. The presented approach uses MATLAB version 7.1.0.246 and Cadence Analog Circuit Optimizer. The results are verified by detailed analog simulation using Cadence Analog Design Environment (ADE from IC 5.0.33) in 0.35µm mixed-mode CMOS process.