High-Speed hardware implementation of rainbow signature on FPGAs
PQCrypto'11 Proceedings of the 4th international conference on Post-Quantum Cryptography
Performance analysis of multivariate cryptosystem schemes for wireless sensor network
Computers and Electrical Engineering
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This paper deals with the design of an area-timeefficient hardware architecture for the multivariate signaturescheme, Rainbow. As a part of this architecture, a highperformancehardware optimized variant of the well-knownGaussian elimination over GF(2l) and its efficient implementationis presented. Besides solving LSEs, the architecture is alsore-used for the linear transformation operations of the scheme,thereby saving on area. The resulting signature generationcore of Rainbow requires 63,593 gate equivalents and signsa message in just 804 clock cycles. A comparison of ourarchitecture with implementations of the RSA, the ECDSA andthe en-TTS scheme shows that Rainbow in hardware providessignificant performance improvements.