Energy-aware hardware implementation of network coding
NETWORKING'11 Proceedings of the IFIP TC 6th international conference on Networking
Quasi-parallel network applications in real-time distribution management system
International Journal of Innovative Computing and Applications
High performance power flow algorithm for symmetrical distribution networks with unbalanced loading
International Journal of Computer Applications in Technology
Exploiting SIMD parallelism on dynamically partitioned parallel network coding for P2P systems
Computers and Electrical Engineering
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It is a well known result that network coding may achieve better network throughput in certain multicast topologies. However, the practicality of network coding has been questioned, due to its high computational complexity. This paper represents an attempt towards a high performance implementation of network coding. We first propose to implement progressive decoding with Gauss-Jordan elimination, such that blocks can be decoded as they are received. We then employ hardware acceleration with SIMD vector instructions. We also use a careful threading design to take advantage of symmetric multiprocessor (SMP) systems and multicore processors. Our core idea of optimization is the table_based multiplication in GF(28) ,which is able to process a row multiplication of random linear codes by searching previous built product tables with vector using the SSE3 instruction PSHUFB. Our high performance implementation is encapsulated as a C++ class library. On a dual-core Intel T5500 1.66G PC, the encoding bandwidth of our implementations able to reach 42.493 MB/second with 128 blocks of 4KB each.