A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors

Authors:
Lars Baunegaard With Jensen;Anders Kjær-Nielsen;Javier Díaz Alonso;Eduardo Ros;Norbert Krüger
Affiliations:
-;-;-;-;-
Venue:
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
Year:
2008

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A two-level real-time vision machine combining coarse- and fine-grained parallelism

Journal of Real-Time Image Processing

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Abstract

This paper describes the hybrid architecture developed for speeding up the processing of so-called multi-modal visual primitives which are sparse image descriptors extracted along contours. In the system, the first stages of visual processing are implemented on FPGAs due to their highly parallel nature whereas the higher stages are implemented in a coarse parallel way on a multicore PC.A significant increase in processing speed could be achieved (factor 11.5) as well as in terms of latency (factor 3.3). These factors can be further increased by optimizing the processes implemented on the multicore PC.