Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration

Authors:
Tameesh Suri;Aneesh Aggarwal
Affiliations:
-;-
Venue:
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Year:
2009

Citing 0
Cited 2

Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration

Proceedings of the 6th ACM conference on Computing frontiers
Boosting single thread performance in mobile processors via reconfigurable acceleration

ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a low-power LDPC decoder design for additive white Gaussian noise (AWGN) channels. The proposed decoding scheme provides constant-time decoding and thus facilitates real-time applications where guaranteed data rate is required. It ...