Session management architecture for implementing an FPGA-based stateful intrusion detection system

  • Authors:
  • Seungyong Yoon;Byoungkoo Kim;Jintae Oh;Jongsoo Jang

  • Affiliations:
  • Electronics and Telecommunications Research Institute, Yuseong-gu, Daejeon, Republic of Korea;Electronics and Telecommunications Research Institute, Yuseong-gu, Daejeon, Republic of Korea;Electronics and Telecommunications Research Institute, Yuseong-gu, Daejeon, Republic of Korea;Electronics and Telecommunications Research Institute, Yuseong-gu, Daejeon, Republic of Korea

  • Venue:
  • ACS'08 Proceedings of the 8th conference on Applied computer scince
  • Year:
  • 2008

Quantified Score

Hi-index 0.00

Visualization

Abstract

This paper relates to session management architecture and mechanism for implementing an FPGA-based stateful intrusion detection system. Our proposed architecture can help to perform Stateful Packet Inspection(SPI) in real time using a new session table management scheme that allows more efficient generation of session state information in intrusion detection system. SPI is an important technique to reduce false positive alerts in network intrusion detection system(NIDS). As the number of session increases, this technique requires a higher processing speed, thereby causing performance problems. However, existing software-based solutions cannot perform real-time packet inspection ensuring the wire speed. To guarantee both performance and functionality with respect to statefulness, we designed and implemented SPI-based intrusion detection module in a FPGA to help alleviating a bottleneck in network intrusion detection systems in this paper.