Negation-Limited Inverters of Linear Size

Authors:
Hiroki Morizumi;Genki Suzuki
Affiliations:
Graduate School of Information Sciences, Tohoku University, Sendai, Japan 980-8579;School of Engineering, Tohoku University, Sendai, Japan 980-8579
Venue:
ISAAC '08 Proceedings of the 19th International Symposium on Algorithms and Computation
Year:
2008

Citing 0
Cited 2

Limiting Negations in Formulas

ICALP '09 Proceedings of the 36th International Colloquium on Automata, Languages and Programming: Part I
Note: Limiting negations in non-deterministic circuits

Theoretical Computer Science

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Abstract

An inverter is a circuit which outputs ¬x1, ¬x 2, ..., ¬xn for any Boolean inputs x1, x 2, ..., xn . Beals, Nishino and Tanaka have given aconstruction of an inverter which has sizeO(nlogn) and depthO(logn) and uses ⌈log(n + 1)⌉ NOT gates. In this paper we give a construction of aninverter which has size O(n) and depth log1+ o(1) n and uses log1 +o(1) n NOT gates. This is the firstnegation-limited inverter of linear size using onlyo(n) NOT gates.