Software Pipelining in Nested Loops with Prolog-Epilog Merging

  • Authors:

  • Mohammed Fellahi;Albert Cohen

  • Affiliations:

  • Alchemy Group, INRIA Saclay, France, and HiPEAC Network,;Alchemy Group, INRIA Saclay, France, and HiPEAC Network,

  • Venue:
  • HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
  • Year:
  • 2008

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Abstract

Software pipelining (or modulo scheduling) is a powerful back-end optimization to exploit instruction and vector parallelism. Software pipelining is particularly popular for embedded devices as it improves the computation throughput without increasing the size of the inner loop kernel (unlike loop unrolling), a desirable property to minimize the amount of code in local memories or caches. Unfortunately, common media and signal processing codes exhibit series of low-trip-count inner loops. In this situation, software pipelining is often not an option: it incurs severe fill/drain time overheads and code size expansion due to nested prologs and epilogs. We propose a method to pipeline series of inner loops without increasing the size of the loop nest, apart from an outermost prolog and epilog. Our method achieves significant code size savings and allows pipelining of low-trip-count loops. These benefits come at the cost of additional scheduling constraints, leading to a linear optimization problem to trade memory usage for pipelining opportunities.