Run-Time Parallelization and Scheduling of Loops
IEEE Transactions on Computers
Compiling and optimizing for decoupled architectures
Supercomputing '95 Proceedings of the 1995 ACM/IEEE conference on Supercomputing
Decoupled access/execute computer architectures
ACM Transactions on Computer Systems (TOCS)
Optimizing compilers for modern architectures: a dependence-based approach
Optimizing compilers for modern architectures: a dependence-based approach
Hacker's Delight
Towards an Optimal Bit-Reversal Permutation Program
FOCS '98 Proceedings of the 39th Annual Symposium on Foundations of Computer Science
Decoupled pre-fetching for distributed shared memory
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
The Closest-to-Mean Filter: An Edge Preserving Smoother for Gaussian Environments
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 4 - Volume 4
Power Efficient Processor Architecture and The Cell Processor
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Sequoia: programming the memory hierarchy
Proceedings of the 2006 ACM/IEEE conference on Supercomputing
CellSs: a programming model for the cell BE architecture
Proceedings of the 2006 ACM/IEEE conference on Supercomputing
Sequoia: programming the memory hierarchy
Proceedings of the 2006 ACM/IEEE conference on Supercomputing
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Streams: emerging from a shared memory model
IWOMP'08 Proceedings of the 4th international conference on OpenMP in a new era of parallelism
Delayed side-effects ease multi-core programming
Euro-Par'07 Proceedings of the 13th international Euro-Par conference on Parallel Processing
Towards metaprogramming for parallel systems on a chip
Euro-Par'09 Proceedings of the 2009 international conference on Parallel processing
Performance analysis of the OP2 framework on many-core architectures
ACM SIGMETRICS Performance Evaluation Review - Special issue on the 1st international workshop on performance modeling, benchmarking and simulation of high performance computing systems (PMBS 10)
Mesh independent loop fusion for unstructured mesh applications
Proceedings of the 9th conference on Computing Frontiers
Design and performance of the OP2 library for unstructured mesh applications
Euro-Par'11 Proceedings of the 2011 international conference on Parallel Processing
Predictive modeling and analysis of OP2 on distributed memory GPU clusters
ACM SIGMETRICS Performance Evaluation Review
Algorithmic species: A classification of affine loop nests for parallel programming
ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
Proceedings of the 6th Workshop on General Purpose Processor Using Graphics Processing Units
Designing OP2 for GPU architectures
Journal of Parallel and Distributed Computing
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On multi-core architectures with software-managed memories, effectively orchestrating data movement is essential to performance, but is tedious and error-prone. In this paper we show that when the programmer can explicitly specify both the memory access pattern and the execution schedule of a computation kernel, the compiler or run-time system can derive efficient data movement, even if analysis of kernel code is difficult or impossible. We have developed a framework of C++ classes for decoupled Access/Execute specifications, allowing for automatic communication optimisations such as software pipelining and data reuse. We demonstrate the ease and efficiency of programming the Cell Broadband Engine architecture using these classes by implementing a set of benchmarks, which exhibit data reuse and non-affine access functions, and by comparing these implementations against alternative implementations, which use hand-written DMA transfers and software-based caching.