Longest path selection for delay test under process variation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Analysis and modeling of CD variation for statistical static timing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
An accurate sparse matrix based framework for statistical static timing analysis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Fast second-order statistical static timing analysis using parameter dimension reduction
Proceedings of the 44th annual Design Automation Conference
CAD-based security, cryptography, and digital rights management
Proceedings of the 44th annual Design Automation Conference
Confidence scalable post-silicon statistical delay prediction under process variations
Proceedings of the 44th annual Design Automation Conference
A general framework for spatial correlation modeling in VLSI design
Proceedings of the 44th annual Design Automation Conference
Variation-aware performance verification using at-speed structural test and statistical timing
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Active hardware metering for intellectual property protection and security
SS'07 Proceedings of 16th USENIX Security Symposium on USENIX Security Symposium
Proceedings of the 45th annual Design Automation Conference
Noninvasive leakage power tomography of integrated circuits by compressive sensing
Proceedings of the 13th international symposium on Low power electronics and design
IEEE Transactions on Information Theory
PSTA-based branch and bound approach to the silicon speedpath isolation problem
Proceedings of the 2009 International Conference on Computer-Aided Design
Proceedings of the 2009 International Conference on Computer-Aided Design
Gate-level characterization: foundations and hardware security applications
Proceedings of the 47th Design Automation Conference
Proceedings of the 47th Design Automation Conference
A unified submodular framework for multimodal IC Trojan detection
IH'10 Proceedings of the 12th international conference on Information hiding
Integrated circuit security techniques using variable supply voltage
Proceedings of the 48th Design Automation Conference
Low-power resource binding by postsilicon customization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Capturing post-silicon variation by layout-aware path-delay testing
Proceedings of the Conference on Design, Automation and Test in Europe
Scalable hardware trojan diagnosis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware trojan design and detection: a practical evaluation
Proceedings of the Workshop on Embedded Systems Security
Hi-index | 0.00 |
We address post-silicon characterization of the unique gate delays and their timing distributions on each manufactured IC. Our proposed approach is based upon the new theory of compressed sensing. The first step in performing timing measurements is to find the sensitizable paths by traditional testing methods. Next, we show that the timing variations are sparse in the wavelet domain. The sparsity is exploited for estimation of the gate delays using the compressed sensing theory. This estimation method requires significantly less number of timing measurements compared to the case where the dependence between the gate delays is not directly integrated within the estimation framework. We discuss a number of applications for the new post-silicon timing characterization method. Experimental results on benchmark circuits show that using compressed sensing theory can characterize the post-silicon variations with a mean accurately of 95% in the pertinent sparse basis.