A high performance LDPC decoder for IEEE802.11n standard

Authors:
Wen Ji;Yuta Abe;Takeshi Ikenaga;Satoshi Goto
Affiliations:
Waseda University, Kitakyushu, Fukuoka, Japan;Waseda University, Kitakyushu, Fukuoka, Japan;Waseda University, Kitakyushu, Fukuoka, Japan;Waseda University, Kitakyushu, Fukuoka, Japan
Venue:
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Year:
2009

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Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

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Abstract

In this paper, we propose a partially-parallel irregular LDPC decoder for IEEE 802.11n standard. The design is based on a novel sum-delta message passing schedule to achieve high throughput and low area cost design. We further improve the design with pipeline structure and parallel computation. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.