Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
Placement and Routing in 3D Integrated Circuits
IEEE Design & Test
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Design tools for 3-D integrated circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 45th annual Design Automation Conference
Toward accurate models of achievable routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hybrid cache architecture with disparate memory technologies
Proceedings of the 36th annual international symposium on Computer architecture
3D GPU architecture using cache stacking: performance, cost, power and thermal analysis
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Cost-aware three-dimensional (3D) many-core multiprocessor design
Proceedings of the 47th Design Automation Conference
Cost-driven 3D integration with interconnect layers
Proceedings of the 47th Design Automation Conference
An RDL-configurable 3D memory tier to replace on-chip SRAM
Proceedings of the Conference on Design, Automation and Test in Europe
Design exploration of hybrid caches with disparate memory technologies
ACM Transactions on Architecture and Code Optimization (TACO)
Fabrication cost analysis and cost-aware design space exploration for 3-D ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Let there be light!: the future of memory systems is photonics and 3D stacking
Proceedings of the 2011 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness
System-level design space exploration for three-dimensional (3D) SoCs
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Post-silicon bug diagnosis with inconsistent executions
Proceedings of the International Conference on Computer-Aided Design
Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis
Proceedings of the International Conference on Computer-Aided Design
Multi retention level STT-RAM cache designs with a dynamic refresh scheme
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Optimization Methods for Post-Bond Testing of 3D Stacked ICs
Journal of Electronic Testing: Theory and Applications
Bridging pre- and post-silicon debugging with BiPeD
Proceedings of the International Conference on Computer-Aided Design
Distributed memory interface synthesis for network-on-chips with 3D-stacked DRAMs
Proceedings of the International Conference on Computer-Aided Design
Cost evaluation on reuse of generic network service dies in three-dimensional integrated circuits
Microelectronics Journal
Future memory and interconnect technologies
Proceedings of the Conference on Design, Automation and Test in Europe
Challenges in verifying an integrated 3D design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
On effective TSV repair for 3D-stacked ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Optimal placement of vertical connections in 3D Network-on-Chip
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Electronic Testing: Theory and Applications
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Three-dimensional integrated circuit (3D IC) is emerging as an attractive option for overcoming the barriers in interconnect scaling. The majority of the existing 3D IC research is focused on how to take advantage of the performance, power, smaller form-factor, and heterogeneous integration benefits that offered by 3D integration. However, all such advantages ultimately have to translate into cost savings when a design strategy has to be decided: Is 3D integration a cost effective technology for a particular IC design? Consequently, system-level cost analysis at the early design stage is imperative to help the decision making on whether 3D integration should be adopted. In this paper, we study the design estimation method for 3D ICs at the early design stage, and propose a cost analysis model to study the cost implication for 3D ICs, and address the following cost-related problems related to 3D IC design: (1) Do all the benefits of 3D IC design come with a much higher cost? (2) How can 3D integration be achieved in a cost-effective way? (3) Are there any design options to compensate the extra 3D bonding cost? A cost-driven 3D IC design flow is also proposed to guide the design space exploration for 3D ICs toward a cost-effective direction.