A Level-Crossing Flash Asynchronous Analog-to-Digital Converter
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
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Tracking the best level set in a level-crossing analog-to-digital converter
Digital Signal Processing
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Level-crossing analog-to-digital converters (LC ADCs) have been considered in the literature and have been shown to efficiently sample certain classes of signals. One important aspect of their implementation is the placement of reference levels in the converter. The levels need to be appropriately located within the input dynamic range, in order to obtain samples efficiently. In this paper, we study optimization of the performance of such an LC ADC by providing several sequential algorithms that adaptively update the ADC reference levels. The accompanying performance analysis and simulation results show that as the signal length grows, the performance of the sequential algorithms asymptotically approaches that of the best choice that could only have been chosen in hindsight within a family of possible schemes.