Compiler-directed dynamic voltage/frequency scheduling for energy reduction in microprocessors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Power and Energy Profiling of Scientific Applications on Distributed Systems
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
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The present study proposes subtask scheduling for lowering average power and preventing peak power violation in multi-core structure. The proposed algorithm is composed of the partitioning step that divides a task into subtasks using the moving average of power consumption and defines patterns through curve fitting, and the scheduling step that allocates the subtasks to cores and applies dynamic voltage and frequency scaling (DVFS). According to the results of experiment, the algorithm decreased the frequency of peak power by up to around 73% and average power consumption by up to around 18% compared to existing algorithms.