On the Effects of Memory Latency and Bandwidth on Supercomputer Application Performance

  • Authors:
  • Richard Murphy

  • Affiliations:
  • Sandia National Laboratories, PO Box 5800, MS-1110, Albuquerque, NM 87185-1110. rcmurph@sandia.gov

  • Venue:
  • IISWC '07 Proceedings of the 2007 IEEE 10th International Symposium on Workload Characterization
  • Year:
  • 2007

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Abstract

Since the first vector supercomputers in the mid-1970's, the largest scale applications have traditionally been floating point oriented numerical codes, which can be broadly characterized as the simulation of physics on a computer. Supercomputer architectures have evolved to meet the needs of those applications. Specifically, the computational work of the application tends to be floating point oriented, and the decomposition of the problem two or three dimensional. Today, an emerging class of critical applications may change those assumptions: they are combinatorial in nature, integer oriented, and irregular. The performance of both classes of applications is dominated by the performance of the memory system. This paper compares the memory performance sensitivity of both traditional and emerging HPC applications, and shows that the new codes are significantly more sensitive to memory latency and bandwidth than their traditional counterparts. Additionally, these codes exhibit lower base-line performance, which only exacerbates the problem. As a result, the construction of future supercomputer architectures to support these applications will most likely be different from those used to support traditional codes. Quantitatively understanding the difference between the two workloads will form the basis for future design choices.