Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder

Authors:
Samar Yazdani;Thierry Goubier;Bernard Pottier;Catherine Dezan
Affiliations:
Lab-STICC, UMR CNRS 3192, Université de Bretagne Occidentale, Brest, France 29200;Embedded Real-Time System Foundations Laboratory, CEA, LIST, Gif sur Yvette Cedex, France F91191;Lab-STICC, UMR CNRS 3192, Université de Bretagne Occidentale, Brest, France 29200;Lab-STICC, UMR CNRS 3192, Université de Bretagne Occidentale, Brest, France 29200
Venue:
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Year:
2009

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Abstract

In this paper, we present an implementation of a turbo product codes (TPC) decoder achieved on a novel Reconfigurable Multimedia Accelerator (RMA). The RMA is based on the principle of hierarchical shared memory storage managed through a dedicated local controller favoring high data throughput, while squeezing round-trip memory latencies. The mapping methodology facilitates the characterization of the RMA for a TPC decoder in terms of the communication and computation resources.