HTM design spaces: complete decoupling from caches and achieving highly concurrent transactions

Authors:
K. Kunal;K. George;M. Gautam;V. Kamakoti
Affiliations:
Indian Institute of Technology Madras, Chennai, India;Indian Institute of Technology Madras, Chennai, India;Indian Institute of Technology Madras, Chennai, India;Indian Institute of Technology Madras, Chennai, India
Venue:
ACM SIGOPS Operating Systems Review
Year:
2009

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Abstract

This paper proposes a Hardware Transactional Memory (HTM) design for multi-core environments. Using a novel technique to keep track of transactional read-write entries, the design provides a holistic and scalable solution to Transactional Memory (TM) implementation issues of context switching, process migration and overflow handling. Another aspect of the design is that it allows transactions to run in a highly concurrent manner by using special techniques to handle conflict resolution, conflict detection and overflows. The feasibility and validity of the proposed design are demonstrated by developing a synthesizable Hardware Description Language (HDL) model of the design and also experimenting on the same with standard benchmarks.