Convex delay models for transistor sizing
Proceedings of the 37th Annual Design Automation Conference
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Timing Yield Estimation from Static Timing Analysis
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Static timing analysis using backward signal propagation
Proceedings of the 41st annual Design Automation Conference
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model
Proceedings of the 42nd annual Design Automation Conference
A general framework for accurate statistical timing analysis considering correlations
Proceedings of the 42nd annual Design Automation Conference
Statistical static timing analysis: how simple can we get?
Proceedings of the 42nd annual Design Automation Conference
Statistical delay computation considering spatial correlations
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Accurate delay computation for noisy waveform shapes
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical logic cell delay analysis using a current-based model
Proceedings of the 43rd annual Design Automation Conference
Analysis and modeling of CD variation for statistical static timing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Accurate waveform modeling using singular value decomposition with applications to timing analysis
Proceedings of the 44th annual Design Automation Conference
Compact modeling of variational waveforms
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Towards a more physical approach to gate modeling for timing, noise, and power
Proceedings of the 45th annual Design Automation Conference
A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Characterization of Standard Cells for Intra-Cell Mismatch Variations
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
PERT as an aid to logic design
IBM Journal of Research and Development
Statistical timing analysis using bounds and selective enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Methodology for Worst-Case Analysis of Integrated Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Weibull-based analytical waveform model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical timing analysis under spatial correlations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical Timing Analysis: From Basic Principles to State of the Art
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A compact variation-aware timing model for a standard cell in a cell library is developed. The cell model incorporates variations in the input waveform and loading, process parameters, and the environment into the cell timing model. The cell model operates on full waveforms, which are modeled using principal component analysis (PCA). PCA enables the construction of a compact model of a set of waveforms impacted by variations in loading, process parameters, and the environment. Cell characterization involves describing with equations how waveforms are transformed by a cell as a function of the input waveforms, process parameters, and the environment. The models have been evaluated by calculating the delay of paths. The results demonstrate improved accuracy in comparison with table-based static timing analysis at comparable computational cost. Complexity of the models as a function of the number of parameters modeling variation is also discussed, and shows reduced memory requirements as the number of parameters describing variations increases.