Good Codes Based on Very Sparse Matrices
Proceedings of the 5th IMA Conference on Cryptography and Coding
Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS
ARVLSI '01 Proceedings of the 2001 Conference on Advanced Research in VLSI
A scalable LDPC decoder ASIC architecture with bit-serial message exchange
Integration, the VLSI Journal
Factor graphs and the sum-product algorithm
IEEE Transactions on Information Theory
Probability propagation and decoding in analog VLSI
IEEE Transactions on Information Theory
IEEE Communications Magazine
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We present a low power, dual-function encode/decode circuit for a class of reversible low-density parity-check codes. The circuit offers a small silicon footprint, by operating as an analog decoder and reusing resources to switch into a digital encode mode. In order to achieve this behaviour from a single circuit we have developed mode-switching gates. These logic gates are able to switch between analog (soft) and digital (hard) computation. Only a small overhead in circuit area is required to transform the analog decoder into a full codec. The encode operation can be performed two orders of magnitude faster than the decode operation, making the circuit suitable for full-duplex applications. The low power and small area of the circuit make it an attractive option for battery powered wireless devices. Circuit simulations indicate a decoding latency of 10@ms with negligible SNR loss with respect to digital sum-product decoders.