Pseudorandom signal sampler for relaxed design of multistandard radio receiver

  • Authors:

  • Chiheb Rebai;Manel Ben-Romdhane;Patricia Desgreys;Patrick Loumeau;Adel Ghazel

  • Affiliations:

  • CIRTA'COM Research Lab, Ecole Supérieure des Communications de Tunis (SUP'COM), Cité technologique des Communications, 2088 El Ghazala, Ariana, Tunisia;CIRTA'COM Research Lab, Ecole Supérieure des Communications de Tunis (SUP'COM), Cité technologique des Communications, 2088 El Ghazala, Ariana, Tunisia and LTCI-CNRS UMR 5141, Ecole Nati ...;LTCI-CNRS UMR 5141, Ecole Nationale Supérieure des Télécommunications de Paris (TELECOM ParisTech), 46, Rue Barrault, 75634 Paris Cedex 13, France;LTCI-CNRS UMR 5141, Ecole Nationale Supérieure des Télécommunications de Paris (TELECOM ParisTech), 46, Rue Barrault, 75634 Paris Cedex 13, France;CIRTA'COM Research Lab, Ecole Supérieure des Communications de Tunis (SUP'COM), Cité technologique des Communications, 2088 El Ghazala, Ariana, Tunisia

  • Venue:
  • Microelectronics Journal
  • Year:
  • 2009

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Abstract

This paper proposes a novel software defined radio (SDR) receiver design using non-uniform sampling (NUS) technique implemented by original design of a pseudorandom signal sampler (PSS) circuit for controlling data conversion to relax multistandard receiver circuit constraints. The proposed and designed NUS-based SDR receiver allows spectral alias suppression at integer multiples of sampling frequency offering the advantages of relaxing anti-aliasing filter (AAF), reducing the analog-to-digital converter (ADC) dynamic power consumption and the automatic gain control (AGC) range as well. The PSS circuit, generating pseudorandom clock signal, with enough time-quantization accuracy, was designed. The PSS is implemented in 65-nm digital CMOS technology and occupies 470(@mm)^2. It features up to 200MHz ''mean clock'' for 3.2GHz main clock while drawing 242@mA for 1.2V supply. Mixed experimental/simulation tests, of designed NUS-based SDR receiver, revealed a confirmation of alias-free performances and the achievement of a 72dB (12-bit ADC) dynamic range after signal reconstruction.