Buffer size design linked to reliability performance: A simulative study

  • Authors:
  • D. Battini;A. Persona;A. Regattieri

  • Affiliations:
  • Department of Management and Engineering, University of Padova, Stradella San Nicola, 3 36100 Vicenza, Italy;Department of Management and Engineering, University of Padova, Stradella San Nicola, 3 36100 Vicenza, Italy;Department of Industrial and Mechanical Plants, University of Bologna, Viale Risorgimento, 2 40136 Bologna, Italy

  • Venue:
  • Computers and Industrial Engineering
  • Year:
  • 2009

Quantified Score

Hi-index 0.00

Visualization

Abstract

Material flow along a Flow Production Line may be disrupted by machine failures or variable processing times. In particular, Automatic Flow Production Lines are often affected by the presence of micro-down-times (i.e. speed losses due to work-pieces blocking or congestion, momentary stiff or stuck pieces on machines, etc.), which can penalize the productivity of the system and increase losses in availability for the whole plant. Moreover, micro-breakdowns cause inability of the system not to respond to sudden changes in demand due to capacity restrictions. Intermediate buffers built between the various machines in an asynchronous automatic (or semi-automatic) production line may increase the reliability of the whole system by limiting the consequences of micro-downtime, and saving companies from making inadequate purchases of oversized equipment. In this paper a new efficiency simulative study for the allocation of storage capacity in serial production lines is developed and a new experimental cross matrix is provided as a tool to determine the optimal buffer size. Thus, this research studies the relationship of machines' availability and buffers size, in order to stress a new paradigm: the buffer design for availability (BDFA). Using a simulation approach, this paper describes the effects of workstation reliability parameters on buffer capacity level, developing a set of simple guidelines to support and help designers and practitioners in the rapid and robust buffer design issue.