On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Realizable and Unrealizable Specifications of Reactive Systems
ICALP '89 Proceedings of the 16th International Colloquium on Automata, Languages and Programming
On the Synthesis of an Asynchronous Reactive Module
ICALP '89 Proceedings of the 16th International Colloquium on Automata, Languages and Programming
Synthesis from Knowledge-Based Specifications (Extended Abstract)
CONCUR '98 Proceedings of the 9th International Conference on Concurrency Theory
A Decidable Class of Asynchronous Distributed Controllers
CONCUR '02 Proceedings of the 13th International Conference on Concurrency Theory
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Games for synthesis of controllers with partial observation
Theoretical Computer Science - Logic and complexity in computer science
Synthesizing Distributed Systems
LICS '01 Proceedings of the 16th Annual IEEE Symposium on Logic in Computer Science
Complexity classification of network information flow problems
SODA '04 Proceedings of the fifteenth annual ACM-SIAM symposium on Discrete algorithms
LICS '05 Proceedings of the 20th Annual IEEE Symposium on Logic in Computer Science
SFCS '79 Proceedings of the 20th Annual Symposium on Foundations of Computer Science
Distributed reactive systems are hard to synthesize
SFCS '90 Proceedings of the 31st Annual Symposium on Foundations of Computer Science
Synthesis of asynchronous systems
LOPSTR'06 Proceedings of the 16th international conference on Logic-based program synthesis and transformation
Church's problem and a tour through automata theory
Pillars of computer science
Distributed synthesis for well-connected architectures
FSTTCS'06 Proceedings of the 26th international conference on Foundations of Software Technology and Theoretical Computer Science
On distributed program specification and synthesis in architectures with cycles
FORTE'06 Proceedings of the 26th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
The MSO theory of connectedly communicating processes
FSTTCS '05 Proceedings of the 25th international conference on Foundations of Software Technology and Theoretical Computer Science
Distributed games with causal memory are decidable for series-parallel systems
FSTTCS'04 Proceedings of the 24th international conference on Foundations of Software Technology and Theoretical Computer Science
IEEE Transactions on Information Theory
Information Tracking in Games on Graphs
Journal of Logic, Language and Information
Taming distributed asynchronous systems
CONCUR'10 Proceedings of the 21st international conference on Concurrency theory
A communication based model for games of imperfect information
CONCUR'10 Proceedings of the 21st international conference on Concurrency theory
Synthesizing strategies for homogenous multi-agent systems with incomplete information
CLIMA'11 Proceedings of the 12th international conference on Computational logic in multi-agent systems
Decidability of well-connectedness for distributed synthesis
Information Processing Letters
Fair Synthesis for Asynchronous Distributed Systems
ACM Transactions on Computational Logic (TOCL)
Asynchronous games over tree architectures
ICALP'13 Proceedings of the 40th international conference on Automata, Languages, and Programming - Volume Part II
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We study the synthesis problem for external linear or branching specifications and distributed, synchronous architectures with arbitrary delays on processes. External means that the specification only relates input and output variables. We introduce the subclass of uniformly well-connected (UWC) architectures for which there exists a routing allowing each output process to get the values of all inputs it is connected to, as soon as possible. We prove that the distributed synthesis problem is decidable on UWC architectures if and only if the output variables are totally ordered by their knowledge of input variables. We also show that if we extend this class by letting the routing depend on the output process, then the previous decidability result fails. Finally, we provide a natural restriction on specifications under which the whole class of UWC architectures is decidable.