International Journal of Parallel Programming
A structural induction theorem for processes
Proceedings of the eighth annual ACM Symposium on Principles of distributed computing
CADE-10 Proceedings of the tenth international conference on Automated deduction
Experiments with proof plans for induction
Journal of Automated Reasoning
Rippling: a heuristic for guiding inductive proofs
Artificial Intelligence
MFPS '92 Selected papers of the meeting on Mathematical foundations of programming semantics
PAM: a process algebra manipulator
Formal Methods in System Design
Communication and Concurrency
Planning Proofs of Equations in CCS
Automated Software Engineering
The Use of Planning Critics in Mechanizing Inductive Proofs
LPAR '92 Proceedings of the International Conference on Logic Programming and Automated Reasoning
A Verification Tool for Value-Passing Processes
Proceedings of the IFIP TC6/WG6.1 Thirteenth International Symposium on Protocol Specification, Testing and Verification XIII
A Computer-Checked Verification of Milner's Scheduler
TACS '94 Proceedings of the International Conference on Theoretical Aspects of Computer Software
Searching for a Solution to Program Verification=Equation Solving in CCS
MICAI '00 Proceedings of the Mexican International Conference on Artificial Intelligence: Advances in Artificial Intelligence
An Interface between Clam and HOL
Proceedings of the 11th International Conference on Theorem Proving in Higher Order Logics
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Concurrency and Automata on Infinite Sequences
Proceedings of the 5th GI-Conference on Theoretical Computer Science
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
The Concurrency Factory: A Development Environment for Concurrent Systems
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
The Use of Explicit Plans to Guide Inductive Proofs
Proceedings of the 9th International Conference on Automated Deduction
Mechanizing a Proof by Induction of Process Algebrs Specifications in Higher Order Logic
CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification
Planning Equational Verification in CCS
ASE '98 Proceedings of the 13th IEEE international conference on Automated software engineering
Unique Fixpoint Induction for Value-Passing Processes
LICS '97 Proceedings of the 12th Annual IEEE Symposium on Logic in Computer Science
Incremental pattern-based coinduction for process algebra and its isabelle formalization
FOSSACS'10 Proceedings of the 13th international conference on Foundations of Software Science and Computational Structures
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Unique Fixpoint Induction (UFI) is the chief inference rule to prove the equivalence of recursive processes in the Calculus of Communicating Systems (CCS) (Milner 1989). It plays a major role in the equational approach to verification. Equational verification is of special interest as it offers theoretical advantages in the analysis of systems that communicate values, have infinite state space or show parameterised behaviour. We call these kinds of systems VIPSs. VIPSs is the acronym of Value-passing, Infinite-State and Parameterised Systems. Automating the application of UFI in the context of VIPSs has been neglected. This is both because many VIPSs are given in terms of recursive function symbols, making it necessary to carefully apply induction rules other than UFI, and because proving that one VIPS process constitutes a fixpoint of another involves computing a process substitution, mapping states of one process to states of the other, that often is not obvious. Hence, VIPS verification is usually turned into equation solving (Lin 1995a). Existing tools for this proof task, such as VPAM (Lin 1993), are highly interactive. We introduce a method that automates the use of UFI. The method uses middle-out reasoning (Bundy et al. 1990a) and, so, is able to apply the rule even without elaborating the details of the application. The method introduces meta-variables to represent those bits of the processes' state space that, at application time, were not known, hence, changing from equation verification to equation solving. Adding this method to the equation plan developed by Monroy et al. (Autom Softw Eng 7(3):263---304, 2000a), we have implemented an automatic verification planner. This planner increases the number of verification problems that can be dealt with fully automatically, thus improving upon the current degree of automation in the field.