Task Scheduling in a Finite-Resource, Reconfigurable Hardware/Software Codesign Environment
INFORMS Journal on Computing
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Modern Field-Programmable Gate Arrays (FPGAs) are becoming very popular in embedded systems and high-performance applications. FPGA has benefited from the shrinking of transistor feature size, which allows more on-chip reconfigurable (e.g. memories and look-up tables) and routing resources. Unfortunately, the amount of reconfigurable resources in a FPGA is fixed and limited. This paper investigates an application-mapping scheme in FPGA by utilizing sequential processing units and task specific hardware. Genetic Algorithm is used in this study. We found that placing sequential processor cores into FPGA can improve the resource utilization efficiency and achieved acceptable system performance. In this paper, two cases were studied to determine the trade-off between resource optimization and system performance.