Proceedings of the 11th Annual conference on Genetic and evolutionary computation
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
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Network Processors (NPs) are embedded system-on-a-chip multiprocessors that are optimized to perform simple packet processing tasks at data rates of several Gigabytes per second. They are the key components to build a performance-scalable and function-flexible network systems. To meet the performance demands of increasing link speeds and more complex network applications, NPs are implemented with several dozen of processor cores and run multiple packet processing applications in parallel. This trend makes it increasingly difficult for application developers to program NPs for high performance. This paper presents an automated task scheduling technique to address this parallel programming complexity. Our proposed technique is based on GA. By incorporating tasks dependency into scheduling list and encoding task scheduling list as a chromosome, GA can quickly remove the invalid mappings and evolve to the high quality solutions. This technique takes advantage of task-level and application-level parallelism to maximize system performance for a given NPs architecture. The simulation results show that this proposed technique can generate high quality mapping comparing to other heuristics by mapping some sample network applications. This work will also enable researchers and engineers to systematically evaluate and quantitatively understand the NPs system issues including application partitioning, architecture organizing, workload mapping and run-time operating.