A flash translation layer for huge-capacity flash memory storage systems

Authors:
Chin-Hsien Wu
Affiliations:
Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan
Venue:
AICCSA '08 Proceedings of the 2008 IEEE/ACS International Conference on Computer Systems and Applications
Year:
2008

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Abstract

The capacity of flash-memory storage systems grows at a speed similar to many other storage systems. In order to properly manage the product cost, vendors face serious challenges in system designs. In this paper, an efficient flash translation layer is proposed with low memory requirements. The objective of the design is to provide efficient address mapping with low garbage collection overhead, provided that memory space requirement for the flash translation layer is properly managed. The capability of the design is evaluated over realistic workloads.