Fine-Grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-threshold-Voltage Transistors

Authors:
Masashi Imai;Kouei Takada;Takashi Nanya
Affiliations:
-;-;-
Venue:
ASYNC '09 Proceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)
Year:
2009

Citing 0
Cited 1

A low-latency adaptive asynchronous interconnection network using bi-modal router nodes

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

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Abstract

To the casual observer, glitches occurring in quasi delay-insensitive logic would appear to cause incorrect operation and render the circuits unusable. This paper presents an informal analysis of the effects of glitches occurring on the long interconnect ...