MACOM'11 Proceedings of the 4th international conference on Multiple access communications
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In the past decades, we have seen exponential increase of a single processor core performance. This was necessary to catch-up with the growing complexity of applications required by the market. Till now, the performance growth was achieved by drastic increase of the processor core clock speed up to current 4.3GHz. Nowadays, the further increase of performance by increasing the clock frequency is not feasible due to power dissipation, leakage and scaling problems. However, the market still demands more and more complex applications. To deal with this demand, all modern processor units consist of multiprocessor System-on-Chip (SoC) with multiple processing cores. The question is, how do we map the modern applications on these modern processors. In this paper, we demonstrate a flow starting from the sequential MATLAB specification going to parallel implementation for a leading-edge 40 MHz Multiple Input Multiple Output (MIMO) Space Division Multiplexing (SDM)-Orthogonal Frequency Division Multiplexing (OFDM) application. We introduce the whole flow to the reader and we focus on the parallelization part. We demonstrate both, the functional parallel model as well as the mapping of the application on the Software Defined Radio (SDR) platform [12] with two instances of state-of-the-art ADRES embedded processor [7]. We show, that when we do the parallelization wisely w.r.t. communication overhead, we can achieve the theoretical gain of factor of two for the SoC with two processor instances.