Processor Performance Modeling using Symbolic Simulation

Authors:
Omid Azizi;Jamison Collins;Dinesh Patil;Hong Wang;Mark Horowitz
Affiliations:
Department of Electrical Engineering, Stanford University;Microarchitecture Research Lab (MRL), Intel Corporation;Department of Electrical Engineering, Stanford University;Microarchitecture Research Lab (MRL), Intel Corporation;Department of Electrical Engineering, Stanford University
Venue:
ISPASS '08 Proceedings of the ISPASS 2008 - IEEE International Symposium on Performance Analysis of Systems and software
Year:
2008

Citing 0
Cited 1

End-to-end performance forecasting: finding bottlenecks before they happen

Proceedings of the 36th annual international symposium on Computer architecture

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper we explore microprocessor performance models implemented on FPGAs. While FPGAs can help with simulation speed, the increased implementation complexity can degrade model development time. We assess whether a simulator split into closely-coupled ...