Metrics for Architecture-Level Lifetime Reliability Analysis

  • Authors:
  • Pradeep Ramachandrany;Sarita V. Adve;Pradip Bose;Jude A. Rivers

  • Affiliations:
  • Department of Computer Science, University of Illinois at Urbana-Champaign, pramach2@uiuc.edu, srinivsn@uiuc.edu;Department of Computer Science, University of Illinois at Urbana-Champaign, sadve@uiuc.edu;IBM T. J. Watson Research Center, Yorktown Heights, NY 10598, pbose@us.ibm.com;IBM T. J. Watson Research Center, Yorktown Heights, NY 10598, jarivers@us.ibm.com

  • Venue:
  • ISPASS '08 Proceedings of the ISPASS 2008 - IEEE International Symposium on Performance Analysis of Systems and software
  • Year:
  • 2008

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Abstract

In this paper we explore microprocessor performance models implemented on FPGAs. While FPGAs can help with simulation speed, the increased implementation complexity can degrade model development time. We assess whether a simulator split into closely-coupled ...