Clock Synchronization in Cell BE Traces
Euro-Par '08 Proceedings of the 14th international Euro-Par conference on Parallel Processing
Cell broadband engine processor performance optimization: tracing tools implementation and use
IBM Journal of Research and Development
Trace-based performance analysis framework for heterogeneous multicore systems
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
SPM-Sieve: a framework for assisting data partitioning in scratch pad memory based systems
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
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In this paper we explore microprocessor performance models implemented on FPGAs. While FPGAs can help with simulation speed, the increased implementation complexity can degrade model development time. We assess whether a simulator split into closely-coupled ...