Fabrication cost analysis and cost-aware design space exploration for 3-D ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
Clock tree synthesis with methodology of re-use in 3D IC
Proceedings of the 49th Annual Design Automation Conference
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Each stratum in a 3D chip usually requires a unique mask set which increases the mask cost for a multi-strata chip compared to its 2D counterpart. We present a novel design technique using reciprocal design symmetry (RDS) that allows a mask set (or at least a majority of these) to be used for different strata while still achieving vertical placement and connection of different design functionalities. We demonstrate an application of RDS using a detailed example of a 3D dual-core microprocessor with analyses of various design complexity and testability issues, and a comprehensive simulation and comparison of its thermal characteristics. The coarse grained partitioning of selfcontained functional units achieved with RDS is suitable for early adoption of 3D technology as well as for long-term application to low cost system integration due to less redesign effort, design tool requirements, and better testability of each stratum before and after bonding.