Place and route considerations for voltage interpolated designs

Authors:
Kevin Brownell;Ali Durlov Khan;David Brooks;Gu-Yeon Wei
Affiliations:
School of Engineering and Applied Sciences, Harvard University, Cambridge, MA 02138, USA;School of Engineering and Applied Sciences, Harvard University, Cambridge, MA 02138, USA;School of Engineering and Applied Sciences, Harvard University, Cambridge, MA 02138, USA;School of Engineering and Applied Sciences, Harvard University, Cambridge, MA 02138, USA
Venue:
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Year:
2009

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Automating design of voltage interpolation to address process variations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

Voltage interpolation is a promising post fabrication technique for combating the effects of process variations. The benefits of voltage interpolation are well understood. Its implementation in a VLSI-CAD flow has been considered through the synthesis stage. In this paper we study the implications of place and route on voltage interpolation. We evaluate multiple placement strategies, and conclude that a hybridization of forced placement and cluster boxing techniques results in minimum overhead.