Process variation-aware performance analysis of asynchronous circuits
Microelectronics Journal
Statistical leakage power optimization of asynchronous circuits considering process variations
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Asynchronous logic is a hot topic due to its interesting features of power saving, low noise and robustness to parameters variations. Beside of the benefits of asynchronous design technique, the lack of automatic design and analysis tools made it hard to apply them in the new designs. Timing analysis is a necessary step in automatic design process and optimization of asynchronous circuits. On the other hand, increasing variation of process parameters of integrated circuits and more sensitivity of today's designs has increased the necessity of statistical approach to timing analysis of asynchronous circuits. So it seems to be necessary to introduce a method to the performance analysis of asynchronous circuits considering the variation in process parameters. In this paper, we present a novel method to analyze the performance of template-based asynchronous circuits statistically. Asynchronous circuit has been modeled using Variant-Timed Petri-Net. Based on this model, the probability density function of the delay of global critical cycle is calculated. The results of the experiments are compared with Mont Carlo simulation-based results and the average error is %2.8 for the mean value of the delays.