Performance-energy tradeoffs in reliable NoCs

Authors:
Ying-Cherng Lan;Michael C. Chen; Wei-De. Chen; Sao-Jie Chen; Yu-Hen Hu
Affiliations:
Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan, ROC;Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan, ROC;Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan, ROC;Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan, ROC;Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI53706, USA
Venue:
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Year:
2009

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Dual-layer adaptive error control for network-on-chip links

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

Today's process technologies place emphasis on low power design in multi-core systems that require the complicate communication networks-on-chip (NoC) architecture to be reliable. Considering the many error control codes (ECCs) implemented in a hardware NoC router, the primary objective of this paper is accounting for the causes of energy consumed for fault tolerance and providing a way of comparison among different ECC methods. To make a proper choice, tradeoff between power and throughput of each ECC achieving the same reliability must be considered. Hence, some low-overhead ECC methods used in NoC have been implemented in hardware and their performance-energy tradeoff shown.