Hardware-software co-design of a speech translation embedded system

  • Authors:
  • Shun-Chieh Lin;Jia-Ching Wang;Hsueh-Wei Yang;Jhing-Fa Wang

  • Affiliations:
  • (Correspd. Tel.: +886 6 384 7482/ Fax: +886 6 384 7182/ E-mail: jason.lin@itri.org.tw) Home Networking Technology Center, Industrial Technology Research Institute, No.31, Gongye 2nd Rd., Annan Dis ...;Department of Electrical and Computer Engineering, University of Wisconsin-Madison, 1415 Engineering Drive, Madison, WI 53706-1691, USA;Multimedia and Communication IC Design Lab, Department of Electrical Engineering, National Cheng Kung University, No.1, Dasyue Rd., East District, Tainan City 701, Taiwan;Multimedia and Communication IC Design Lab, Department of Electrical Engineering, National Cheng Kung University, No.1, Dasyue Rd., East District, Tainan City 701, Taiwan

  • Venue:
  • Journal of Embedded Computing - Design and Optimization for High Performance Embedded Systems
  • Year:
  • 2009

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Abstract

Previous research has shown that there are two architectures for speech-to-speech translation (S2ST) system implementation. One is client-server based systems that are built on the server computer, which means they are not available anytime or anywhere. The other is portable stand-alone devices, which lack real-time performance. Therefore, this work presents a hardware-software co-design of a speech translation embedded system for portable S2ST applications. This system is characterized by small size, low cost, real-time operation, and high portability. In order to realize the proposed S2ST system, we have designed the ARM-based system-on-a-programmable-chip (SoPC) architecture, the speech translation intellectual property, and the software procedures of the proposed SoPC. The entire design was implemented on ALTERA EPXA10. The English-to-Mandarin translation process can be completed within 0.5 second at a 40 MHz clock frequency with 1,200 translation patterns. The maximum frequency is 46.22 MHz, and the usage of logic elements is 19,318 (50% of the total number of logic elements of the EPXA10 device).