A low-power baseband modem architecture for a mobile RFID reader

  • Authors:

  • Seok Joong Hwang;Joon Goo Lee;Seon Wook Kim;Jihun Koo;Woo Shik Kang

  • Affiliations:

  • Compiler and Microarchitecture Laboratory, School of Electrical Engineering, Korea University, Seoul, Korea;Compiler and Microarchitecture Laboratory, School of Electrical Engineering, Korea University, Seoul, Korea;(Correspd. School of Electrical Engineering, Korea University, 5 ka-1, Anam-dong, Sungbuk-ku, Seoul 136-701, South Korea. E-mail: seon@korea.ac.kr) Compiler and Microarchitecture Laboratory, Schoo ...;Communication and Network Laboratory, Samsung Advanced Institute of Technology, Korea;Communication and Network Laboratory, Samsung Advanced Institute of Technology, Korea

  • Venue:
  • Journal of Embedded Computing - Design and Optimization for High Performance Embedded Systems
  • Year:
  • 2009

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Abstract

Currently the RFID (Radio Frequency IDentification) systems become used in many areas, especially for delivery, manufacturing, and maintenance of goods. For example, a tag reader or a tag interrogator communicates with tags attached on goods, reads their identification codes, and accesses their related database through a network infrastructure. This approach makes it easy to maintain goods very efficiently in large-scale markets, delivery systems, and so on. There are many research activities in RFID systems for industrial applications, but there is few on mobile and portable devices such as cellular phones and PDAs. This paper presents an architecture overview of a multi-protocol RFID reader on mobile devices with detailed description of hardware implementation. We have considered several design parameters, such as low power consumption, cost effectiveness and flexibility. Also, since our architecture supports WIPI (Wireless Internet Platform for Interoperability), any WIPI application can use our RFID reader's functionalities to query tags' information from Internet through HAL interfaces. We prototyped our system on the ARM-based Excalibur FPGA with iPAQ PDA, and also a chip with 0.18~um technology for verification of our architecture.