MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A Reconfiguration Manager for Dynamically Reconfigurable Hardware
IEEE Design & Test
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Efficient datapath merging for partially reconfigurable architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Run-time reconfiguration can increase the cost efficiency and hardware specialisation of reconfigurable processors by dynamically changing the configuration of the reconfigurable logic to the required functionality. In this paper, we propose a scheme for managing the run-time reconfiguration of custom instructions on a partially reconfigurable architecture that incorporates multi-bit logic blocks. The proposed scheme relies on the dynamic execution profile to replace the functionality of the logic blocks with the goal of minimising the overall reconfiguration overhead. Experimental results show that the proposed scheme for run-time customisation can lead to an average speedup of three times and average area savings of over 30% when compared to a method that relies on compile-time customisation.