SOC chip interconnect embodying I-slip algorithm

• Authors: Neetu N. Gyanchandani;Vilas A. Nitnaware
• Venue: ISPRA'09 Proceedings of the 8th WSEAS international conference on Signal processing, robotics and automation
• Year: 2009

With the improvement in fabrication technology, smaller feature size allow more integration of system components onto a single die, hence communication becomes limiting factor for performance, so we need a design so that the efficiency of interconnect increases. This can be achieved by On-chip interconnect embodying I-slip algorithm for efficient communication between 8 soc devices This algorithm is derived from slip algorithm which is an improvement upon the round robin scheduling algorithm. The design described consists of implementation of the three main blocks of a 8 by 8 input buffered crossbar switch or interconnect: the input block, scheduler block and finally the output block. All the blocks are implemented in VHDL using xilinix tool project navigator and modelsim software. The interconnect is capable of handling 72 bit packets and a total of 32 packets at a time. There are total 8 devices and we have to establish the communication between them. Each device consists of an input block and the output block. The input block first receives the 72 bit packet and the total of 32 packets one by one. The input block internally consists of four arrays-destination head, destination tail, packet array and linked list array and also a shift register. It stores the packets in an array called packet array. When scheduler sends transmit request these packets are given to the scheduler. Scheduler internally consists of grant and accept arbiters. Scheduler performs its operation in three steps i.e request, grant and accept. It works on the principle of i-slip algorithm. Finally the scheduler decides that which packet should be send from the input block to the output block of the device. Output block of the device simply receives the packet. These packets are send and received in two phases. In the first phase 36 bits are send and in the second phase 36 bits are send. Thus the connection is established between the devices using interconnect. Using these optimization techniques the design is able to achieve best timing and area, also this interconnect design provides fast communication and full N-to-N routing capabilities. Thus this interconnect acts as a switch connecting input blocks to output blocks.