NSP: a Neuro---Symbolic Processor

Authors:
Ernesto Burattini;Massimo Gregorio;Victor M. Ferreira;Felipe M. França
Affiliations:
Dipartimento di Scienze Fisiche, Università degli Studi di Napoli "Federico II", Complesso universitario di Monte Sant'Angelo, Napoli, Italy I80126;Istituto di Cibernetica "Eduardo Caianiello", Pozzuoli (NA), Italy I80078;Department of Informatics Graduate School of Information Science and Electrical Engineering, Kyushu Univ., Fukuoka, Japan 816-8580;Programa de Engenharia de Sistemas e Computação, PESC/COPPE, Universidade Federal do Rio de Janeiro, Rio de Janeiro, RJ, Brazil Caixa Postal 68511 21945-970
Venue:
IWANN '03 Proceedings of the 7th International Work-Conference on Artificial and Natural Neural Networks: Part II: Artificial Neural Nets Problem Solving Methods
Year:
2009

Citing 3
Cited 3

NeuroSymbolic Processing: Non-Monotonic Operators and Their FPGA Implementation

SBRN '00 Proceedings of the VI Brazilian Symposium on Neural Networks (SBRN'00)
NSL: a Neuro-Symbolic Language for Monotonic and Non-Monotonic Logical Inferences

SBRN '02 Proceedings of the VII Brazilian Symposium on Neural Networks (SBRN'02)
Computation: finite and infinite machines

Computation: finite and infinite machines

An Intelligent Active Video Surveillance System Based on the Integration of Virtual Neural Sensors and BDI Agents

IEICE - Transactions on Information and Systems
An adaptive oscillatory neural architecture for controlling behavior based robotic systems

Neurocomputing
ISIDIS: an intelligent videosurveillance system

Proceedings of the International Working Conference on Advanced Visual Interfaces

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents an implementation methodology of weighted ANNs whose weights have already been computed. The validation of this technique is made through the synthesis of circuits implementing the behaviour of specialised ANNs compiled from sets of logical clauses describing different logical problems. ANeuro---Symbolic Language (NSL) and its compiler5have been designed and implemented in order to translate the neural representation of a given logical problem into the corresponding VHDL code, which in turn can set devices such as FPGA(Field Programmable Gate Array). The result of this operation leads to an electronic circuit called NSP (Neuro---Symbolic Processor) that effectively implements a massively parallel interpreter of logic programs.