Optimization of a lattice Boltzmann computation on state-of-the-art multicore platforms

  • Authors:

  • Samuel Williams;Jonathan Carter;Leonid Oliker;John Shalf;Katherine Yelick

  • Affiliations:

  • CRD/NERSC, Lawrence Berkeley National Laboratory Berkeley, Berkeley, CA 94720, United States and CS Division, University of California at Berkeley, Berkeley, CA 94720, United States;CRD/NERSC, Lawrence Berkeley National Laboratory Berkeley, Berkeley, CA 94720, United States;CRD/NERSC, Lawrence Berkeley National Laboratory Berkeley, Berkeley, CA 94720, United States;CRD/NERSC, Lawrence Berkeley National Laboratory Berkeley, Berkeley, CA 94720, United States;CRD/NERSC, Lawrence Berkeley National Laboratory Berkeley, Berkeley, CA 94720, United States and CS Division, University of California at Berkeley, Berkeley, CA 94720, United States

  • Venue:
  • Journal of Parallel and Distributed Computing
  • Year:
  • 2009

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Abstract

We present an auto-tuning approach to optimize application performance on emerging multicore architectures. The methodology extends the idea of search-based performance optimizations, popular in linear algebra and FFT libraries, to application-specific computational kernels. Our work applies this strategy to a lattice Boltzmann application (LBMHD) that historically has made poor use of scalar microprocessors due to its complex data structures and memory access patterns. We explore one of the broadest sets of multicore architectures in the high-performance computing (HPC) literature, including the Intel Xeon E5345 (Clovertown), AMD Opteron 2214 (Santa Rosa), AMD Opteron 2356 (Barcelona), Sun T5140 T2+ (Victoria Falls), as well as a QS20 IBM Cell Blade. Rather than hand-tuning LBMHD for each system, we develop a code generator that allows us to identify a highly optimized version for each platform, while amortizing the human programming effort. Results show that our auto-tuned LBMHD application achieves up to a 15 times improvement compared with the original code at a given concurrency. Additionally, we present a detailed analysis of each optimization, which reveals surprising hardware bottlenecks and software challenges for future multicore systems and applications.