3D floorplanning of low-power and area-efficient Network-on-Chip architecture
Microprocessors & Microsystems
| Hi-index | 0.00 |
We have entered the era of many-core processors and complex SoCs, where on-chip interconnection networks play a dominant role in determining the performance, power, and ultimately cost of a system. Therefore, interconnection strategy that supports efficient communication between IP blocks is essential. Any communication model can be well characterized by locality properties and, any topology has its intrinsic, structural, locality characteristics. We propose a new criterion in performance evaluation that is based on the concept of group locality in an interconnection network, the “lower layer complete connect”. Our proposed criterion depicts how completely a processing node is connected to all its neighbors. In this paper we evaluate TriBA, a class of direct interconnection network (DIN), for multi-core on-chip interconnection architecture. TriBA is compared with 2D Mesh as static interconnection networks for VLSI implementation. The criteria of evaluation are enumerated from two orthogonal view points, viz., computational speed and physical layout. We conclude that TriBA has the potential to have significantly better performance as an on-chip interconnection network for future MPSoC systems.