Brief announcement: performance potential of an easy-to-program PRAM-on-chip prototype versus state-of-the-art processor

Authors:
George C. Caragea;A. Beliz Saybasili;Xingzhi Wen;Uzi Vishkin
Affiliations:
University of Maryland, College Park, MD, USA;NIH, Bethesda, MD, USA;NVIDIA Corporation, Santa Clara, CA, USA;University of Maryland, College Park, MD, USA
Venue:
Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures
Year:
2009

Citing 2
Cited 4

Parallel Quicksort Using Fetch-And-Add

IEEE Transactions on Computers
Fpga-based prototype of a pram-on-chip processor

Proceedings of the 5th conference on Computing frontiers

Lazy binary-splitting: a run-time adaptive work-stealing scheduler

Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
Algorithmic approach to designing an easy-to-program system: Can it lead to a HW-enhanced programmer's workflow add-on?

ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Using simple abstraction to reinvent computing for parallelism

Communications of the ACM
Algorithm engineering: bridging the gap between algorithm theory and practice

Algorithm engineering: bridging the gap between algorithm theory and practice

Quantified Score

Hi-index	0.02

Visualization

Abstract

We compare the Paraleap FPGA computer, a 64-processor hardware prototype of the PRAM-driven XMT architecture, with an Intel Core 2 Duo processor and show that Paraleap outperforms the Intel processor by up to 13.89x in terms of cycle counts. The comparison favors the Intel design, since the silicon area of an ASIC implementation of the 64-processor XMT design is the same as that of a single core.